PCB Design Rules 101 - Phil's Lab #170

In this video, I'd like to cover the basics of PCB design rules. Where PCB

design rules don't really tell us how to route out or how to lay out a certain PCB, but rather the design rules when it comes to PCB design tell us the constraints and the limits that we have

when routting when laying out and when designing our printed circuit boards.

For instance, here I have the PCB rules and constraints editor window open within Altium Designer. And every e-cat tool or PCB design tool will have something similar to this where you can edit various constraints, the design

rules if that is how narrow or how wide your traces are allowed to be, how far apart your pads are allowed to be, what nets should be using impedance control and much much more. And in this video, I will guide you through the basics of

this. Design rules are there so that we

this. Design rules are there so that we when we are designing printed circuit board for instance the one we are seeing here that this PCB adheres to certain constraints and these are oftentimes governed by your manufacturer whatever

you're designing for if it's for aerospace defense consumer electronics and so on the complexity of the PCB if you're trying to make a lowcost PCB and so on. Design rules essentially are the

so on. Design rules essentially are the basics of making a functioning safe and manufacturable PCB with hopefully high reliability and high manufacturing yield. So for instance, if you just end

yield. So for instance, if you just end up sending this design for manufacturing to a PCB manufacturer of your choice, if they make 100 boards, of course you would want close to 100 of these boards to actually then be functioning without

defects and hopefully also low cost compared to the complexity of the design. And this depends on a lot of how

design. And this depends on a lot of how we set up our design rules and how we tailor them again to our manufacturer to certain standards and industry and application we are designing for. Design

rules are often times very much design dependent. I rarely use the same set of

dependent. I rarely use the same set of design rules twice for boards. I will

adjust depending on complexity. If I

need impedance control, how many layers I have, if I'm doing true via PCBs, I'm doing highdense interconnect PCBs. These

constraints and rules I set up here will differ depending on the design. It'll

also differ depending on not just the PCB complexity, but also if this is for consumer electronics, if it's for the medical space, if it contains high voltage elements, I need creepage and clearance constraints and so on. what I

enter here. These numbers aren't just pulled from thin air. There's a lot of design rules you can set up. You can set up global design rules. You can set them up for certain spaces on your PCB. For

instance, you're just planning out a QFN or BGA package. And in only that certain area, you need you need less constraining design rules and everywhere else you use more strict design rules.

All of that is possible in most PCB and ECAD tools. The design rules, as we saw

ECAD tools. The design rules, as we saw briefly, define for instance, geometrical constraints, how close objects can be to each other, for instance, how close traces can be to each other, how the solder mask

expansions are, how close I can put silk screen to expose copper. There are many, many different design rules, and again, we will go through them in this video.

Other than that, there could also be electrical constraints. For instance, if

electrical constraints. For instance, if I have high voltage nets, I need a certain spacing between other conductors such as creepance and clearance constraints. If I have controlled

constraints. If I have controlled impedance routting, for instance, in this time in this design, I have high-speed USB 3.0 and gigabit Ethernet, the traces I route out here have to adhere to certain electrical rules as

well based on a stackup and based on impedance constraints. Also, when it

impedance constraints. Also, when it comes to assembly, we might have a different set of constraints. We might

have a constraint that says only allow components on the top layer because we only want assembly on one side. It might

be to do with test points. It can be to do how closely we allow our components to be placed next to each other. So

there are many different areas for these design rules. I'll show you how to get

design rules. I'll show you how to get these design rules and derive them from manufacturers, but oftent times you can also get them from IPC standards, from for example, milspec standards and so on, whatever industry and whatever

product you're working for and with.

Again, this video is just a primer on design rules. As you get more experience

design rules. As you get more experience with PCB design, you know which rules you can adjust, what you can set for certain areas, what you need to pay attention to. But it's incredibly

attention to. But it's incredibly important that you set up your design rules before you start layout and start routting your PCB. What you definitely don't want to have happen is that you start placing and rooting out components, sending this board off to

manufacturer and the manufacturer coming back to you and saying we can't manufacture this or we can only manufacture this with an increased cost because you use tiny v you use tiny trace features and it's very very difficult to manufacture. So make sure

you set this up, make sure you understand design rules before you begin with layout and routting of your PCB cuz that'll save you a lot of time, effort, and hassle. A huge thank you to JLC PCB

and hassle. A huge thank you to JLC PCB for sponsoring this video. A lot of the information we will cover in this particular video also pertains to the manufacturing capabilities of JLC PCB.

And we'll see how JLCPCB helps us as PCB designers to get the relevant information we need on the manufacturing capabilities, their stackup and impedance control and much much more. I

have most of my PCBs manufactured at GLC PCB and they always do a fantastic job.

In particular, I would like to shout out the high precision six layer PCB service. Six layer PCBs give you access

service. Six layer PCBs give you access to more routin layers of course than two or four layers. Increases your routing efficiency. You can have dedicated

efficiency. You can have dedicated ground and power planes on extra signal layers giving you faster development cycles, cleaner design and fewer redesigns. Typically JLC PCB helps us

redesigns. Typically JLC PCB helps us out as designers because of an unbeatable price. For instance, for a

unbeatable price. For instance, for a six layer PCB 50x 50 mm, we can get them right now at $2 for five pieces. And

this includes an immersion nickel gold surface finish. We can specify impedance

surface finish. We can specify impedance control and we get epoxy filled and capped V as a standard. So we can do VN pad again just for $2 for 50x 50 mm PCBs. I'd strongly suggest checking out

PCBs. I'd strongly suggest checking out JLC PCB. They often times offer coupons

JLC PCB. They often times offer coupons also for new users and I'll leave links to these in the description box below. A

huge thank you also to Alim for sponsoring this video. I use Alim Develop which includes Alum Design and Alim 365 in my everyday day-to-day work life as well as for creating content for

this channel. Out in develop enables

this channel. Out in develop enables multiddisciplinary teams to design, develop and manufacture highquality hardware products with ease and efficiency all the way from co-creation of designs be that parts library

management, schematic design, hardware design, requirements management, all the way through managing your supply chain, manufacturing and of course generating and maintaining all of the relevant data

as part of an entire project. You can

take a tour of Alton Develop and I'll leave links to this in the description box below which guides you through all of the parts that Alton Develop helps you manage in your project and product design process if you're interested.

Again, I'll leave links in the description box below, but you can get started with Alton Develop and you can try this out for yourself risk-f free for 30 days. Links will be in the description box below. When I start a

new PCB design, the first thing I would set up, which I believe are part of the design rules, is the layer stack up and layer assignment. Even if you're not

layer assignment. Even if you're not doing controlled impedance, even if you're just doing a simple two-layer board, I set up these parameters in my ECAD tool. And most ECAD tools, if not

ECAD tool. And most ECAD tools, if not all of them, should let you do this. In

Altium Designer, for instance, I can go to design layer stack manager. And for

this particular board, this is actually a four layer board. Here we can see the stack up underneath the stackup tab where I choose if I have silk screen top and bottom, what type of surface finish I want, copper thicknesses for the

various layers, layer names, preer types, dialectric types, core types, and so on. This information later on when I

so on. This information later on when I have this board manufactured, I would then send along to my manufacturer.

Often times, it's a communication between you and your manufacturer to figure out what stackup is possible, what you need for your certain impedance constraints, if you have impedance constraints, and so on. So I definitely recommend making a note of this also for

yourself. This might include the total

yourself. This might include the total thickness as well, which is important.

If you didn't have complex requirements for your stackup, if any two layer, any four layer stackup is fine, I would still suggest putting this in your ECAD tool for the sake of completeness. A lot

of the design rules might also link to your stackup. For instance, that you're

your stackup. For instance, that you're only allowed to root on the outer layers and the inner layers should just be solid reference plane with with no rooting. A lot of the design rules can

rooting. A lot of the design rules can reference your stackup. So I'd suggest setting up that stackup first. This

particular stackup, similar to the design rules, I did not pull for out of thin air. Again, either speak to your

thin air. Again, either speak to your manufacturer, reuse stackups you've used in the past, which you know are manufacturable for your particular requirements. In my case, I got this

requirements. In my case, I got this from the JLC PCB website because this is where I had this printed circuit board manufactured and assembled. Regardless

of which manufacturer you use, they will have this information either publicly available on their website or you have to send them a mail or get in contact with them to retrieve this information.

Luckily for me and for us, JLCPCB has that on their website. We can go to get quote and if we for instance select a four layer PCB like we have in this design. Scrolling down a bit we can

design. Scrolling down a bit we can select specify stackup. If I click yes various stackup options are available and these are standard stackups that JLC PCB provides. Some of them cost more

PCB provides. Some of them cost more because there might be non-standard stackups but for instance the in quotes no requirement stackup which is essentially the same as the 7628 stackup will have these various this stackup. So

we have copper of a certain thickness.

We have a certain pre prag type in a layer copper and so on. And this is then what I would transfer over to my ECAD tool before I then continue setting up the design rules. Other than having design rules that are dependent on the

stackup, of course, we will also have in many designs controlled impedance requirements. And you will need to know

requirements. And you will need to know your stackup to determine the trace widths and spacings you need to achieve those targeted impedances. That's also

the case for this particular design. So

I chose a particular stackup that fits with my design with my particular trace width requirements. I got this from the

width requirements. I got this from the JLC website. And once I transferred this

JLC website. And once I transferred this particular stackup over, this is their four layer 3313 stackup. The next step for me while I'm still in this layer stackup view is going to the impedance tab and setting up my controlled

impedances. In this design, I needed a

impedances. In this design, I needed a single end of 50 ohms. I need a differential 90 ohms for USB and I need a differential 100 ohms. And you can see here I've entered the trace width and

trace gaps. Item designer quite nicely

trace gaps. Item designer quite nicely calculates the trace impedances using a 2D field solver, but you should rely on your manufacturer to give you the final answer. But in this way I also have

answer. But in this way I also have impedances defined which later on we can set up as design rules with corresponding net names. For example

pointing to the USB differential pairs I can say when I start routting out USB differential pairs make sure to use differential 90 impedance profile. So

that's why I strongly suggest setting up your stackup setting up your impedances first before you continue then to your design rules because they are dependent on each other. Nice thing is with JLC PCB, depends on the manufacturer, they

actually have an online calculator for the impedances which you can use. I just

wanted to give that a brief shout out even though it's not terribly relevant to this video. You will need to set up your stackup and often times your control impedances as well because of course you will need this before you

start layout and routting. Okay, in

certain scenarios you might not know how many layers you need until you've started rooting out and you figure out okay will I need four, six or whatever number of layers. But often times from experience you'll have a good idea given

the components of the design, given the components within the design, given the space constraints within the design, how many layers approximately you might need. So it could be that some point

need. So it could be that some point throughout the design you'll have to adjust your stackup and you would just go through that process again. But I

would strongly suggest at least having an initial stackup which lets you then route out, set up your ground planes, your structure and so on. So that would be my first step with the stackup carried over and our controlled

impedance requirements. if you have any

impedance requirements. if you have any moved over to your ECAD tool, we can now begin looking at the actual design rules themselves and how we can translate them. For instance, from your

them. For instance, from your manufacturer's manufacturing capabilities into your ECAD tool. Again,

as we talked about in the beginning, these might not come from your the design rules might not come from your manufacturer. They might be a

manufacturer. They might be a combination from your manufacturer's capabilities as well as whatever you're designing for and what the standards you're designing towards. If that's

certain IPC standards, if it's military aerospace, consumer electronics, that will change how you implement your design rules. Especially when it comes

design rules. Especially when it comes to things such as RF or high voltage systems, you'll have to pay of course even more attention, but that's the topic for future video. This is again just a design rules 101, the absolute

basics of design rules and how you can implement them and use them quite quickly in your own PCB designs. Before

we get into more specifics, we will set up global design rules. And later on, we'll also look at using design rules with net classes. For instance, saying these are impedance controlled nets only use the certain design rules with these

type of nets. And we'll look at that with net classes. And later on, we'll also look at implementing for the case of aluminum designer, these are called rooms. So certain areas where different design rules can apply. This is very

useful, very localized design rules where you might want to relax your constraints a tiny bit in a certain area, but leave the overall global design rules in place. Again, I can't stress enough that you should not start

a PCB design layout rooting without having defined your design rules properly. You don't want to stick with

properly. You don't want to stick with the default design rules that open up that are there when you create a new PCB document. You want to set these design

document. You want to set these design rules up properly. They will save you a lot of hassle in the long run. Secondly,

you'll probably want to try this out for yourself. Looking at your manufacturer

yourself. Looking at your manufacturer of choice, you might have a different PCB design constraints, different area you're designing for. What I can also suggest is that you stay away from

absolute minimums unless you really need to. If your manufacturer can do 0.09 mm

to. If your manufacturer can do 0.09 mm trace widths, it does not mean you should be using that and it definitely should not mean you should be using that all the time. Again, very much design dependent, but try and stay away from

design manufacturing minimums. Generally, if that's traced with solar mass or whatnot, the manufacturers are trying to show you what they can do if absolutely required. Staying away from

absolutely required. Staying away from that will increase your yield, will increase the chances of most of your PCBs after being manufactured will end up working correctly or at least having been manufactured correctly. With that

being said, it pays off to look at the basic design rules in place. If I go to design and then rules and aluminum designer for different e-card tools, that's of course located somewhere else.

Every PCB design software will have this. There are several areas of design

this. There are several areas of design rules again have electrical. This could

be clearance design rules for instance track to track spacing, SMD pad to track spacing, throughhole pad to track spacing and any combination of elementtoelement spacing. Those are your

elementtoelement spacing. Those are your clearance constraints. We can see those

clearance constraints. We can see those in action on the printed circuit board.

If I just go to 2D view, I have certain spacing for instance between a track and a pad that have to be at least or above the design rule constraint we specified.

We have similar constraints between vas and traces. We have similar constraints

and traces. We have similar constraints between holes and traces and so on. So

that's what's meant with these clearance constraints. Essentially just

constraints. Essentially just geometrical physical spacing constraints between different features. We don't

just have one overall clearance constraint. So that's any object to any

constraint. So that's any object to any other object because the manufacturing process are different. For creating

traces or copper features, we will typically have etching. Whereas for

creating holes, you might have drills.

So different size drill bits which might have drill wonder. So you might not so the manufacturer won't be able to drill with such precision that we know exactly the via will be drilled in this particular area. The drill will have

particular area. The drill will have some wonder will have some tolerance and a finite precision. That's why we have these design rules because we can't be 100% accurate 100% precise and that depends on what type of feature the

manufacturer is building. Again, if

we're drilling, if we're etching, if we're applying solder mask or if we're applying silk screen, all of these have different tolerances and different processes. So, it's important that we

processes. So, it's important that we have separate clearance constraints and not just one overall. And that again, we can see in the design rules because we have this table here, this matrix where we have various clearance constraints to

each other where you can get these clearance constraints from. I'm using

JLCPCB for this particular design. If I

go to the capabilities section, again, most PCB manufacturers will have this online or you can contact them. If I

scroll down and go for instance to traces, we can see minimum track width and minimum track spacing. And this

would be in our case what we want to look for. So they have a capability of

look for. So they have a capability of 0.10 mm. That's 4 mil in imperial units.

0.10 mm. That's 4 mil in imperial units.

But we also can read further on the right hand side. One and two layer PCBs have 0.1 mm constraints. But multi-layer

PCBs, so four layers and above, actually you can go slightly lower. And again,

this is an absolute minimum trace width and trace spacing that you can use.

Suggested to stay away from that unless you absolutely need to use this. We can

also see another comment which will be relevant for us later that in certain areas, for example, if you're fanning out a BGA or very tightly spaced package, you can also go down to 3 mil,

so even lower than 0.09 mm. So, what you would then do is you take that information, again, an absolute minimum, and move that over to your PCB design constraints. Here you can see my trackto

constraints. Here you can see my trackto track spacing I've set at.127

because.127 is 5 mil. So I like to have this crossover that I can use imperial and metric and I typically type in the metric equivalent of the imperial even though that might sound a bit mad. I

could of course round.13 but this is I have this nice crossover between imperial metric depending on what PCB manufacturer I send this to. In any case you can see I've stayed away from the

0.1 or 0.09 09 mm trace spacing minimum.127. I know 5 mil is something

minimum.127. I know 5 mil is something that pretty much most manufacturers can do if it's a two or four layer PCB. It

isn't necessarily a cost adder. Having

this low of a trace to trace spacing does not typically add cost to a PCB design. Most manufacturer can do this

design. Most manufacturer can do this comfortably. And in addition, I need

comfortably. And in addition, I need this trace spacing. For instance, for this QFN package or for this ESD, these TVs do diodes. I have some very narrow spacing between these pads and between

these traces and I need to have a design rule that can accommodate that and enough this is still quite a bit above the absolute minimum that for instance JLC can produce. Therefore, I take my absolute minimum from the manufacturer

and add on quite a considerable margin.

I could of course go up to 2 mm if my design allows. You want to set that at

design allows. You want to set that at the lowest that is comfortable for your design but not any lower. You can then go through and fill in similar fields.

for example, track to SMD pad, track to throughhole pad and so on. And you would take this information from your PCB manufacturer's capabilities. It'll also

manufacturer's capabilities. It'll also typically have a drawing which indicates what you actually looking at. So here we see minimum trace to trace spacing, the minimum trace width. And these don't just depend on the number of layers. It

also depends on what copper thicknesses you use, which again references back to setting up your stack up early. If you

know you're going to have a high current design, if you're limited to the number of layers and you actually have to increase the copper thickness of certain layers, that will influence what trace width and trace spacing you can use depending on the copper thicknesses you

have to use. We also get information on the trace width tolerances, which would be important for impedance control, for example. From this information,

example. From this information, scrolling down the list, you can fill in all of this clearance information.

That's fairly self-evident what you need to extract from your manufacturer. In

addition to the clearance, what's closely linked if we go to the routting design rules is the routting width.

Whereas we saw the trace spacing and trace width parameters were quite closely linked. Again, depending on the

closely linked. Again, depending on the manufacturers's capabilities, what copper thicknesses you use, how many layers you have, you will have different constraints, but I would usually set my clearance same as my minimum width. As

we can see clearance, I have.127 mm.

Therefore, my minimum width is.127. You

can set a preferred width. So if you just start a route rooting from a pad out designer might start rooting out with 35 mm and you can also set a maximum width for example and you can set that depending on the layer. I can't

emphasize this enough stay away from manufacturing minimums. You want to only set the minimum width as a global setting that you actually need in the design. If you're only going to be

design. If you're only going to be using.3 mm traces, if you're using large

using.3 mm traces, if you're using large 0603805 components, you're using for example sic packages, you do not need to go down to something like this like.127 mm. You

could go to point 2 or 3. You want to make your manufacturer's life as easy as possible and you can do that by increasing the strictness of your design rules even though your manufacturer states they can do that. In the

clearance section, you might have already seen that we have a lot of copper to copper clearance rules. That's

track to track. It's SMD pad to track.

It's the through hole pad to track and so on. But we also have non-copper

so on. But we also have non-copper clearance rules. For example, text. This

clearance rules. For example, text. This

is our silk screen. This isn't silk screen or it could be whole clearances.

And these will be different than your copper to copper clearances because again they use different manufacturing processes. Again you can get this

processes. Again you can get this information from your manufacturer. For

instance you can see here the via hole to track is 0.2 mm minimum. Pad track

clearances are all listed here. There

are several different rules and constraints depending on what features you're looking at and that's very important. One thing that's also

important. One thing that's also outlined here in the JLC PCB section is that it also depends on if you're rooting on outer layers or internal layers what type of clearances you might have. For example, inner layer via hole

have. For example, inner layer via hole to copper clearance might be different than an outer layer via hole to copper clearance. In this case, it actually

clearance. In this case, it actually turns out it isn't, but it's something to take into account that the processing of internal layers versus outer layers can be different as well. That could

mean different manufacturing capabilities. Regardless, I'd strongly

capabilities. Regardless, I'd strongly suggest you check out these various clearance rules that your manufacturer provides and you port them over to your preferred ECAT tool. And you can also save those design rules for future use

or you can use PCB design templates.

Other than the clearance and width rules, which arguably are some of the most important design rules, we also have various other design rules in place and you can get quite into detail depending on what your ECAD tool provides and you can also create custom

rules if you have very specific requirements. Some other rules I would

requirements. Some other rules I would like to cover which I typically use before we move into specific rules for example based on net classes or certain rooms and areas are also to do with manufacturing of course as pretty much

all of these design rules are but for instance the solder mass expansion rule which is very important to set. Often

times people just leave this as a default and that is how much the solder mask is pulled away from exposed copper.

For instance, if I increase this to let's say 2 mm. Click okay. We can see if I change the contrast view that around these exposed copper pads the solder mask essentially a protective

film on the PCB that typically will have this green color is pulled away around these pads. And that's because the

these pads. And that's because the solder mask doesn't have perfect alignment. Again, it's a manufacturing

alignment. Again, it's a manufacturing process. So, the smaller your solder

process. So, the smaller your solder mask expansion is, the closer the solder mask will actually end up being to this exposed copper pad. If you're unlucky and the manufacturing process doesn't go

as wanted, the solder mask can slip onto the exposed copper area, meaning you have less surface area to solder to. And

especially for very small pads, this can be very problematic because you already have not very much solder area to to begin with and you don't want any solder mask to get on top of that. On the other hand, you don't want your solder mask

expansions to be that large because solder mask can also help against bridging with closely spaced pads. For

example, this QFN package here, you don't want to have your solder mask completely removed between these individual pads because that could cause or enable bridges, solder bridges to appear more easily. So, ideally, you

want to have a pretty small solder mass expansion. One that but one that your

expansion. One that but one that your manufacturer can support. Going to gelc again going to the solder mask section.

There are various different parameters to solder mask. Nice enough, as of last year of making this video, JLCPCB increased their capabilities that they can actually do a onetoone solder mask

expansion. So, the solder mask should in

expansion. So, the solder mask should in theory line up exactly with the pad. I'm

sure JLCPC can do this, but I'm still wary and I still want to stay away from absolute manufacturing minimums. So, it will typically increase my solder mass expansion value. Going to the design

expansion value. Going to the design rules. I typically will change that to 3

rules. I typically will change that to 3 mil, which in millimeters is 0.076 mm.

Sometimes I'll go larger at 0.1 millimeters as a default rule. And this

then enables these rather small openings around these exposed copper areas. And

most manufacturers can do this 3M expansion. Other than the sold mass

expansion. Other than the sold mass expansion, we also have minimum solderm bridges which are also known as solder mass webs. JLC nicely illustrates this

mass webs. JLC nicely illustrates this on the right hand side. Between these

various pads, for example, the QFN package we saw in the design. We want

solder mask to run between these pads because that reduces the chances of solder bridges, solder paste bridges and solder bridges. This depends on the

solder bridges. This depends on the color and it depends on the thickness of copper you use. As we can see here, the minimum solder mask bridge or web we're allowed or sliver is 0.1 mm for these

colors. But for black and white, it

colors. But for black and white, it jumps up to 0.13 mm. So be wary of which color you use. You will also have to keep that in mind when you're applying your design rules. Whereas for 2 oz

copper, we actually need 0.2 2 mm of solder mass bridge. Again to illustrate this would be this web or this sliver that goes between the solder mass openings for instance the QFN package but of course it could be also

underneath the resistors or small components. That is the bridge or this

components. That is the bridge or this sliver they are talking about. If we go to design rules again scroll down to manufacturing we can see that in the minimum solder sliver section. I've set

this to 0.1 mm and this is based on this minimum pad spacing. I'm going to have a green PCB made. So I've chosen 0.1 mm in this case. I think it's fine to stick to

this case. I think it's fine to stick to absolute minimums and I do need this 0.1 mm because of my QFN package otherwise I would have to open this whole solder mask aperture. You have something

mask aperture. You have something similar for the paste mask expansion. So

for the solder paste but typically you should go into communication with your manufacturer and they might adjust the paste mask depending on their experiences with assembly and different parts different items. So I typically

leave that as default. Various other

rules that you should be aware of are for instance the polygon connect style.

I use polygon pores rather than the alcheium planes. I find the alcheium

alcheium planes. I find the alcheium planes a bit problematic. So that's why I use polygons and traces. And for this there's a separate rule if you want to do thermal relieves and often times it's a good idea. Of course it depends on the

scenario. But here you can define how

scenario. But here you can define how you want your polygon pores to connect to various circuit elements. If we're

connected to through holes, you can select you want a relief connect, if you want a direct connection, and if you're doing relief, what your air gap width is and your conductor width, how many spokes you have and what orientation

those spokes should be. Similar for SMD pad connections and for via connections.

For through hole and SMD pad unless you have very specific reason I typically always do relief connect and for via connections I do direct connect. Now I

would then manually override those rules. For instance you can see I have

rules. For instance you can see I have no relief on the top side here of this small polygon pore puddle. Whereas on

the bottom side of this one capacitor I have a thermal relief and that's governed by these design rules. The

reason is the copper balance is important. On the bottom side of this

important. On the bottom side of this capacitor, we have this large ground plane, this very heavy thermal mass connected to one side. And if we just did a solid connection on this part, we might get assembly and solder issues for

this very small component, it would skew because one side heats up quicker than the other does. If for instance, you're doing manual assembly. For reflow, it's a bit different. And therefore, you might want to have specific rules or you can override rules. So for instance in

Alene Designer I can select one of these pads go to properties on the right hand side scroll down select relief checkbox and then I can change the thermal relief

to direct and that is on a pad by pad or a casebyase basis and that can override these rules in very specific scenarios.

That doesn't mean because you set up a rule you have to stick with that everywhere. Other than that we also have

everywhere. Other than that we also have hole size constraints which are very important. You don't want to go below a

important. You don't want to go below a minimum hole size. Smaller holes are typically more expensive. Anything below

about.3 mm or 0.25 mm typically encourage a larger manufacturing cost.

Now in volume it might not make much of a difference but it also helps with the yield. Typically having larger holes. So

yield. Typically having larger holes. So

0.25 is a minimum I've set here and as a maximum 6.2. You can of course get

maximum 6.2. You can of course get larger holes but you might not use a drill bit. You might use need to use a

drill bit. You might use need to use a router tool instead to make those holes.

Again check your manufacturer for details. Hole to hole clearances you can

details. Hole to hole clearances you can set here. minimum solder mass liver we

set here. minimum solder mass liver we already saw but also silk to solder mask clearance or silk to solder mass opening is very important we can see here we have different checking modes check

clearance to exposed copper again the alignment of silk screen depending on the process isn't perfect there will be some tolerance if I were to place my silk screen for example so close in the

e-cat tool this looks in quotes great because it's not overlapping the exposed copper but of course there will be some variations to the manufacturing process that could cause the silk screen to overlap with exposed copper. You can

prevent that by setting appropriate design rules, but you can also prevent that by placing your silk screen further away to begin with. And also, your manufacturer should be checking your designs and they should not print solder

mask directly on exposed copper because that can cause assembly issues if they actually go through with that. Often

times they don't. Often times they will check it, but you should be in charge of your design. So that's why that rule is

your design. So that's why that rule is also very important even though electrically it might not seem like it's doing very much. We have net antenna rules that we don't have floating v or traces or just single in traces. That's

important as well. And you can define minimums for that. Board outline

clearance is very important. I typically

will set that at at least 0.3 mm. If

it's a routed board, a 0.3 mm clearance is typically okay. 0.4 mm if it's for vcoring, but I like to stay above that.

So I typically set a 0.5 mm clearance.

Again, you have a whole table matrix here where you can do that for different elements, but I like to stay fairly generic with this clearance rule at 0.5 mm. And as the name implies that's just

mm. And as the name implies that's just any feature if that's copper, if it's a component, what else cannot go past this 0.5 mm clearance rule towards the board edge. This is for depanalization. This

edge. This is for depanalization. This

is just for manufacturability. Another

very important rule and these are predominantly manufacturing based rules.

The ones we just looked at. Other than

that we have more electrical focused rules. And then we can see this in this

rules. And then we can see this in this high-speed segment here. We can create net classes saying this is a high-speed net. This is gigabit ethernet. This is

net. This is gigabit ethernet. This is

USB3 super speed. And we can create rules for those net classes. If I click here, we can say between these two nets, between these two traces, I don't want to have long parallel runs because long parallel runs typically means more

induced cross talk from an aggressor to a victim. And you can implement these

a victim. And you can implement these rules here. You can say you don't want

rules here. You can say you don't want certain length of stubs. We can have a return path rule, which means there should always be a certain width of return path underneath a trace and a certain gap allowed. These are not

manufacturing rules strictly speaking.

They're more electrical rules. And this

can help you when you design your PCB that you stay within these high-speed design constraints with these electrical constraints. So, as a rough overview,

constraints. So, as a rough overview, these are the main rules you might want to consider on a PCB design. You don't

have to set up all of them, but you should definitely set up the core rules such as clearance, width, solder mask, silk screen, and hole sizes, and so on.

the ones we examined in this video.

There are many, many more which you can set up depending on your specifications and what you're designing for and towards. Other than having these rather

towards. Other than having these rather generic global rules which are completely fine to have, you can of course have multiple sets of rules that apply to various different aspects of

your design. A simple example I've added

your design. A simple example I've added here in the clearance section, I've named these rules clearance ground layer 1 and clearance ground layer 4. And

these only apply to the top and bottom ground floods that I've done after I've rooted my main parts of the PCB. So I'm

using the top and bottom layer predominantly for signal and power and the rest then at the end I'm filling with ground and I'm stitching them to my internal ground planes with a number of VAS. In particular, because of these

VAS. In particular, because of these controlled impedance traces, any copper that gets close to these controlled impedance traces can and will, depending how close it is, will throw off the

actual impedance value for these traces that we've so carefully calculated and rooted before. To do that, I want to

rooted before. To do that, I want to pull back the ground pour from these components and from these traces. In

general, typically whenever I flood ground, I have different constraints and different rules for those flooded ground fills compared to just having my internal ground planes and ground

layers. Those have different rules. And

layers. Those have different rules. And

the way we can do that is again go to design rules. For example, create a copy

design rules. For example, create a copy of our general clearance rules, give it a sensible name, and then we can use these PCB design filters to filter out

specific areas or sections. For

instance, if I drop this if I select this drop down, I can select net and layer. I want these rules only to apply

layer. I want these rules only to apply to the ground net which I've labeled in my schematic in my PCB design and I only want that to have on layer 4. I could of course create a custom query where I say

this is ground net and on layer 4 or on layer 1 rather than making two rules for example. In this way then this rule only

example. In this way then this rule only applies to net ground and layer 4 and then these constraints dominate. The

question is when they dominate and the way we can do that is by setting the priorities using the priorities button at the bottom. We want those more specific rules to have a higher priority. So those are set and followed

priority. So those are set and followed first before we then follow these less localized more global design rules. So

we can move the priorities around of these various design rules depending on our requirements. In this way then my

our requirements. In this way then my constraints for layer 2 and layer three ground are different to my external layer ground fills. As we can see here, the clearance is substantially larger

compared to my inner layer ground rules for example. So that's one way of

for example. So that's one way of setting different design rules simply by creating additional rules, selecting filters and then changing the various constraints and design rules for those

particular areas. Another place we might

particular areas. Another place we might want to have different design rules is for various nets. This could be certain power nets. For example, this VBS net,

power nets. For example, this VBS net, we might want to have a larger minimum trace width. Or for these controlled

trace width. Or for these controlled impedance nets, we actually want to route with the controlled impedance that we set out in our stackup manager and our impedance control manager. For this,

we need to give our nets net classes and ideally names as well. Of course, I typically label all of my nets in my designs, but I also add net classes. In

art designer, I can do that with one of these blankets and then one of these directives. If I click on the directive

directives. If I click on the directive and go to properties and then on the right hand side you can click on add net class and then I can give it a net class name. So this net class is now called

name. So this net class is now called USB. So everything that is contained

USB. So everything that is contained within this blanket assigned by this directive is given the net class USB. I

can place directives and net classes by going to directives parameter set differential pair blankets and so on.

And most design tools should be able to do this. Similarly I could also filter

do this. Similarly I could also filter on the net name. So this net name is Vbus because I've placed the Vbus flag and this information on the schematic transfers over to the PCB and there I

can then set very specific rules. So

going back to the PCB design layer one we can see all these green traces just visually are my high-speed USB differential pairs and super speed differential pairs. If I go to design

differential pairs. If I go to design rules go to differential pair rooting I click on for instance the USB differential pairs we have an option at the top where the object matches. I can

choose differential pair class or certain differential pairs or layers and custom queries for instance based on net names and I've selected my USB net classes or differential pairs that I've

defined in the schematic which I've then imported over to the PCB design. Then I

can check use impedance profile and I've selected my differential 90 ohm impedance profile that we saw closer to the start of this video and that's where that interplay is between the stackup control impedance and design rules. So

anytime I then route my USB differential pairs, they will follow that impedance stackup. If my impedance stackup

stackup. If my impedance stackup changes, I will of course have to reroute these pairs. This does not happen automatically, but it's a nice check that out tells you some of these constraints change the st the control

impedance parameters change. For

instance, you can do the same thing also for power nets. If I go to design rules, if I create a new width rule, I could for example call this width power and then I could choose net. I always start

my power net with a plus or minus unless it's ground I could say VB bus and I want to change the minimum width.3

maximum width to 0.1 and preferred width.3 as well. So anytime I then route

width.3 as well. So anytime I then route my Vbus net that would have a minimum width of.3 mm rather than the minimum

width of.3 mm rather than the minimum width we set at.127. Of course you have to set up your priorities as well to make sure the rule priorities are in the order you want them to be in. So in this

way you can really tailor your design rules to help you with the design to make sure you are staying within the parameters you want and you achieve the electrical and manufacturing performance that you desire rather than just manufacturing. Again we have these

manufacturing. Again we have these electrical rules that we can set that are in some way linked to these manufacturing rules. Again it's just an

manufacturing rules. Again it's just an aid a very very useful aid to help you create the best PCB design you can. And

I strongly suggest you use these. Other

than custom rules that apply for instance to a certain net, you might have certain areas where you want to relax your design rules and your design constraints but only a certain physical

area. This could be for BGA or grid

area. This could be for BGA or grid array packages or even for something like a QFN package that we're seeing here. Everywhere else around the PCB, we

here. Everywhere else around the PCB, we don't have particularly stringent requirements. we can have fairly strict

requirements. we can have fairly strict design rules, but close to the QFN, we have these narrow spacings, fairly narrow pads where in this area, we might want to define just a room or a section

where we can use smaller trace widths.

We can use narrow spacings and so on.

The way we would do that in Alum Designer and again different ECAD tools will offer this as well is using rooms. The way we can do that is go to design rules. Right at the bottom under

rules. Right at the bottom under placement room definition, we create a new rule. Then click on this new rule

new rule. Then click on this new rule and I'll just give it a different name.

Let's say room definition QFN. And I'll

click on define on the top layer. And I

can draw an arbitrary shape around this QFN. Right click to finish. And this is

QFN. Right click to finish. And this is now defined this XY coordinate area on the top layer for this particular room.

You might have noticed in the top this query is just says false. And this

indicates to aluminum designer that this room definition this particular area does not control the position of any components. This is purely just an area

components. This is purely just an area that we can then apply different rules to. So we've created a room. We've

to. So we've created a room. We've

selected the area we want that to. And

now we can create custom queries like we saw before for instance for the different net classes based on this particular room. Then with our room

particular room. Then with our room defined, we've given it a name. You

could just call this for example room QFN or whatever makes sense. We can then go back. Let's say create a new

go back. Let's say create a new clearance rule. So I'll just create a

clearance rule. So I'll just create a duplicate of that rule. Give it a somewhat sensible name. And then we have to apply those clearance parameters to that room. The way we can do that is go

that room. The way we can do that is go to the first object matches custom query and type in within room. And then our room props up here as room definition qfn. And then we can type in different

qfn. And then we can type in different clearance constraints. So I could say

clearance constraints. So I could say our track to track spacing is smaller here. SMD to track spacing is smaller

here. SMD to track spacing is smaller here. Again we have to change the

here. Again we have to change the priorities and we want to move our priority higher than our base or global clearance constraint. Click close. And

clearance constraint. Click close. And

you can apply these room rules also any other rule you can find. If you want to be able to use smaller VAS just in that particular room or narrower traces or whatever you can do that using rooms in automat

tools allow you to do something very similar. So within now this room we can

similar. So within now this room we can see this slightly shaded area. I could

within this area just as an example I can actually get much closer to other traces. Now, if I just measure this

traces. Now, if I just measure this distance, this is 0.1 mm because within that room, because I've defined this additional clearance area just within that certain section. So, this can be

very, very helpful if you've got fairly strict rules everywhere else on the PCB and just within certain areas, you want to relax those rules because otherwise you can't root out or can't lay out

certain components and elements. For

instance, having set up your design rules if I were to route out a trace rather than the software let me go anywhere and you see these clearance and con boundaries around various components depending on what we set up that we have

to adhere to. So I could of course hug all of these traces and just route along here. Doesn't look very pretty, but it

here. Doesn't look very pretty, but it would still technically fit the design rules we set up. Now, even though you set up the design rules correctly and you've given yourself clearances and margins based on your manufacturer's

guidelines, that does not mean you need to hug everything and route everything together. You still want to follow, of

together. You still want to follow, of course, common sense and and best PCB design practices, keeping clearance, keeping spacing, and so on. Your design

rules don't protect you from bad design PCB design practices. They are more manufacturing constraints for the most part. So, instance, here I would still

part. So, instance, here I would still want to root out far away from any of these design rule boundaries. And this

of course does not just apply to traces.

It applies to your layout, where you place your VA, where you place your components, how you connect them together. All of these are governed

together. All of these are governed overall by design rules. But you still as a PCB designer have to follow PCB design best practices and use your training to create a good PCB. Again,

the design rules will not protect you from this. Once you've finished your

from this. Once you've finished your PCB, and I would strongly suggest doing this throughout the PCB design, layout, and routting process, you wanted to run a design rule check. So even though we

saw all of these outlines and boundaries happening as we were rooting, not everything is checked for because that would take a long time if this were live and a lot of processing power. So again,

depending on the e-card tool, in my case, I would go to tools, design rule check, shortcut TDR, and then run the design rule check. And what you want to have in particular at the end of the design before you generate any

manufacturing files is you do not want to have any warnings and any violations.

If you do have warnings, if you do have violations, you want to resolve them.

You might have to move things around a bit. You might have to reroute sections

bit. You might have to reroute sections of the design, adjust your layout. And

that's why I strongly suggest running the design check periodically throughout the design rather than just one to the end before I'm ready to generate manufacturing files. It saves you a lot

manufacturing files. It saves you a lot of time and prevents you from having quite a few headaches from doing it. So

otherwise, only when you have no warnings, no design checks, and you've checked everything you want to then proceed to generating manufacturing files, assuming you've checked the rest of the design as well and are happy with it. Thank you very much for watching

it. Thank you very much for watching this video. I hope it was helpful and I

this video. I hope it was helpful and I hope it showed you the basics of PCB design rules, how to set them up, how to extract them and convert them from your manufacturer's capabilities and then also how to go into detail when

assigning design rules based on certain net classes based on your stackup controlled impedance requirements and then also honing in looking at certain rooms and sections and adjusting your PCB design rules for those sections.

Design rule setup is incredibly important. I can't stress that enough

important. I can't stress that enough and you should do that before you begin laying out and routting a PCB. And

you'll get more and more familiar with this as you progress through your PCB design journey. If you like the video,

design journey. If you like the video, please leave a like, a comment if you have any questions, and don't forget to subscribe to stay up to date with any latest PCB design, embedded systems, and DSP videos. Thanks again for watching,

DSP videos. Thanks again for watching, and I hope to see you in the next one.

Bye-bye.