(Sponsored) PCB Power Distribution Networks (PDN) Basics & Measurements - Phil's Lab #161

In this video, I'd like to expose you to the basics of power distribution networks as they appear in real world PCBs and hardware design. We're going to characterize a real world power distribution network as shown in this particular image with this board. We're

going to measure the impedance profile versus frequency and see what effects all these capacitors, regulators, and loads have on the system on the impedance profile. I'll of course show

impedance profile. I'll of course show you why this is important and some of the basics of power distribution networks and also how to model a power distribution network such as the one we are seeing in the printed circuit board we'll be using in this video how to

model the equivalent parameters of all these capacitors traces and so on and then we'll compare and contrast the modeled versus measured systems power distribution networks and their design is a huge topic in itself and we'll only

be scratching the surface but I hope it exposes you to the main elements and shows you why this is important showing you equivalent circuits and most importantly how You can extract that information from pretty much any real

world PCB. A huge thank you to JLC PCCB

world PCB. A huge thank you to JLC PCCB for sponsoring this video. I had these power distribution network test PCBs manufactured and assembled by JLCPCB and they always do a fantastic job. It's

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layers is only $2. And even eight layers at the time of making this video is only $2. And this includes enig surface

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can do VN pad. Plus you can add impedance control and much much more depending on your requirements. PCB

assembly is also super affordable and very easy to set up. Once you've

uploaded your Gerber files, enable the PCB assembly option, upload your bill of materials and component placement files and that's pretty much it. GLC PCB

overall is super easy to use, very affordable, and very, very reliable. If

you'd like to give JLC PCB a try, they typically have coupons available, and I'll leave some links to them in the description box below so you can check out their advanced six layer PCBs, for example. In this video, I'd like to go

example. In this video, I'd like to go over the basics of power distribution networks and in particular, how to measure power distribution networks on realworld PCBs and what the effects of

power distribution networks and their impedance profile are on the system performance and how that can be adjusted and changed. Keep in mind power

and changed. Keep in mind power distribution networks and the topics of measurement and what we're going into is a vastly huge field and we are just scratching the surface. But I hope this video gives you a good intuition of what

is important and why we need this and why you should know about this when you're designing hardware for both analog and digital systems. What I've drawn on this particular image is a very simplified view of a typical power

structure on a printed circuit board. We

have some sort of power source on the left hand side. This might be coming from a battery. whatever is powering the system that typically feeds in some sort of regulator and here I've put a low dropout linear regulator which has input

and output capacitors then we route a bit with a short power trace and because this trace is not ideal we might have some serious resistance and some serious inductance which both depend on the

length and parameters such as width material and so on of the trace on your PCB you might have some bulk decoupling capacitors which might be a large electrolytic another power trace this might be longer shorter again with

serious resistance in series inductance that then feeds into a local decoupling capacitor. You might know them as these

capacitor. You might know them as these 100 nanofharad caps that you place close to IC power pins and then that goes in to let's say the VCC pin of an integrated circuit maybe in microcontroller and FPJ or so on. Keep

in mind this is incredibly simplified.

I've just shown this for one single VCC connection. I'm not showing the non

connection. I'm not showing the non ideal ground connections. I'm showing

simplified models of the capacitors and inductors and so on. But this is just to get the basics. These kind of structures can be extracted from pretty much any PCB, any power distribution network. And

this is exactly what this is. This is

the distribution of power. How we get from the power source to an adequate voltage and feed that into the IC which has certain current and voltage and power demands. Your IC might be running

power demands. Your IC might be running at 3.3 volts and it might have a tolerance that is allowed of 3.3 volt plus minus 100 molts. So it's important and not just at DC but also at AC for

example when this integrated circuit is sourcing or syncing current that the voltage seen at the IC power pin or even on the die of the IC doesn't fluctuate

out of that operating range. So 3.2 to 3.4 volts and FPJs or some other more advanced integrated circuits will have even more stringent voltage rail requirements and might have very high

current requirements in short periods of time. So how do you ensure that your

time. So how do you ensure that your power distribution or your power that has to go through all of these components, all of these non idealities such as serious resistances, inductances and you still keep those margins, those

voltage levels and can sync and source that required amount of current in that typically short amount of time. How do

you ensure that and how do you measure that that system would even work? And

that's where we come into the whole topic of power distribution networks.

Power distribution networks aims to measure what the integrated circuit pin sees looking back towards the power source. And the way we can simplify that

source. And the way we can simplify that is by taking this whole circuit at the top looking at the power pin and looking backwards towards the source. And I've

drawn this incredibly simple somewhat equivalent circuit below. From the IC power pins point of view, from the VCC pin, we're looking back and we're seeing an impedance that depends on frequency.

So if the IC is drawing current let's say periodically at a particular frequency the impedance looking back towards the power source might look like so but the power source this DC source on the left hand side is an AC ground.

So this is the simplified equivalent circuit. Once we've measured this

circuit. Once we've measured this impedance profile of the power distribution network and replaced it with this equivalent circuit we get an impedance versus frequency plot. This is

important because it then shows us what the equivalent series resistance is between the power source and the IC power pin at a certain frequency.

Expanding on that idea, then if we have our DC power source and we have this complicated power distribution network in between, we replace it with just a series resistance that's dependent on

frequency and we model our IC pin as a load resistor with a switch that switches a particular frequency. We can

see that actually the voltage which is seen in the power pin of the IC. This is

top right part of this diagram is part of a voltage divider. A voltage divider between the load of our IC and the series resistance of the power distribution network that is fed by the input voltage source. So depending on

frequency we will have a different series resistance and we'll have a different voltage drop and therefore different VCC voltage depending on what the integrated circuit is doing and depending what our power distribution network looks like. So if you have a

particularly strong load current demand and you have a particularly high impedance of the PDN at a particular frequency that the IC pin is drawing current at, you might get a too large of a voltage drop. You might get brown outs. Your system might malfunction. You

outs. Your system might malfunction. You

might have EMI issues, signal integrity issues, and much much more. Therefore,

it's incredibly important to know what your PDN structure looks like and how to optimize it for a particular hardware design. Typically, we want to aim for a

design. Typically, we want to aim for a low impedance and particularly a flat impedance profile without any particular excursions around a mean value of impedance. You might have heard of

impedance. You might have heard of targeted impedance before, which is relation to how much voltage excursion can we accept at a power pin of an integrated circuit compared to the current demand. And if you divide that

current demand. And if you divide that voltage by that current, that is your target impedance. Very, very simply

target impedance. Very, very simply speaking. So, we typically want to have

speaking. So, we typically want to have a low impedance, not arbitrarily low and not arbitrarily high. There are specific values for this. And we typically want this flat without any peaks and particularly large troughs. This is all well and good, but how do we even know

what this impedance profile looks like?

We've got so many different elements.

And I'm saying to you, well, you can just model that as a simple frequency dependent impedance. And I'll show you

dependent impedance. And I'll show you exactly how to do that in this video using several different methodologies using a BOD 100 vector analyzer as well as an oscilloscope and a function generator. Along the way, we will then

generator. Along the way, we will then see what effects the various traces, caps, and planes have on the power distribution network profile, how we can size them, and what parameters alter the power distribution network profile. So,

to me, I find this super fascinating, really interesting stuff, and very, very relevant to real world hardware design.

Before we go over to some real hardware, I think it's important for you to see, if you haven't before, what a typical plot of impedance versus frequency of a power distribution network looks like

and what is responsible for the shape typically of these plots. What we'll be seeing later in the actual measurement is a graph of impedance magnitude on the y-axis versus frequency on the x-axis.

You'll also often times see a phase versus frequency plot as well to complete the body diagram, but magnitude is typically more important. Here's u

just an example PDN plot that I've just pulled from the internet from the signal integrity journal and I'd strongly suggest checking that out along with anything that Steve Sandal does. He's an

expert on power integrity and has completed vast amounts of research and work on this area. Just to illustrate what we'll be seeing later on, we briefly talked about target impedance that there's a little formula here at

the top. There are different frequency

the top. There are different frequency bands to a power distribution network.

And from our basic model with these non ideal caps and traces and power sources and regulators, all these different components contribute differently to the impedance magnitude across frequency.

For instance, for the lower frequencies up to usually around 10 to 20 kHz with the power regulator on VRM, the voltage regulator module or power management IC PMIC that will dominate the low

frequency impedance of our PDN impedance plot. After that the bulk capacitors

plot. After that the bulk capacitors take over and keep the impedance profile hopefully low above 10 kHz to about 1 MHz. Then we have the smaller capacitors

MHz. Then we have the smaller capacitors because they have lower ESL typically and lower ESR so equivalent series inductance and equivalent series resistance. And these are typically also

resistance. And these are typically also placed closer to the point of load. So

that's why these dominate typically the impedance profile at higher frequencies before we move on to the ondie capacitance on integrated circuits which we as PCB designers aren't typically in

control over of course and after some point we always will end up in some sort of inductive region where the inductance dominates as we'll see later on. Now you

can see already here we might have some resonances where for instance the traces and capacitors resonate together or you might have some troughs which are to do with resonances for instance the

self-ressonant frequencies of capacitors. So you often times see

capacitors. So you often times see parallel and series resonances and keeping the impedance flat can be quite difficult and you typically will have some excursions but it's important to

keep those excursions low because they can trigger what is known as rogue waves and introduce more noise at those points. But we'll see that a bit more

points. But we'll see that a bit more later on. Before we move over to

later on. Before we move over to measuring and characterizing the board, we of course should know what this board is all about. This PDN2 port test board I designed simply to provide a very

easily test all power distribution network which has various elements that we can exchange and see how for instance bulk capacitors, different regulators, different filtering capacitors or series elements and different loads will affect

the impedance profile of a power distribution network. This is purely for

distribution network. This is purely for demonstration purposes and provides very easy calibration systems and very easy test points to measuring at the point of load and that's why this was designed.

And in future videos we will measure so to speak real PCBs for example with have microcontrollers or FPJs on them and see how we can extract the same information from PCBs where the access points are much harder to get to. So this is for

demonstration purposes. We have an input

demonstration purposes. We have an input part where we can feed in from for instance a lab power supply. We can have some serious filtering bulk decoupling before we feed into low dropout linear regulator with its input and output caps

and feedback network. We feed with known trace dimensions that is lengths, widths and distance from reference planes and so on through some bulk decoupling caps.

We follow a longer trace into a filtering element and then into some decoupling capacitors as well as some load resistors. And that point right at

load resistors. And that point right at the bottom here is our point of load which should simulate or emulate an integrated circuit pin which has some larger and some smaller capacitors and has a load as well but for the sake of

this board provides some easy measurement points for our two port shunt through measurement method and we'll go into more detail later on. In

this way we have known components we have known trace lengths and widths that we can measure which we can then use to simulate for example in LT spice and compare that to our real measurement results. So this is a nice controlled

results. So this is a nice controlled environment. The schematic is of course

environment. The schematic is of course very similar as well. We have our input.

We have various filtering elements, various capacitors that we can place or can cannot place. We have a low dropout regulator with feedback, various other capacitors, filtering elements and so on. The whole idea of this board was

on. The whole idea of this board was that it is suitable for the two port shunt through test measurement and that it is very flexible. So we can play with different filtering elements as before and see what the effect is on the impedance profile and to see what the

effect is on the impedance profile. And

I've got calibration points as well as point of load points that interface very nicely with my test and measurement setup which we'll see later on. This is

the board then in real life. And you can see I've made a couple modifications.

I've shorted out the ferad bead because we're not looking at ferad beads in this video. So I shorted out ferad bead one,

video. So I shorted out ferad bead one, ferad bead 2. Also with the measurements in this video, I've actually eliminated C8 and C9. So we only have the 10 microfarad capacitor. We've got the two

microfarad capacitor. We've got the two load resistors R4 and R5. And the rest is pretty much the same. and we have a fixed app voltage of U1 being at 1.8 volt. Before you continue on with this

volt. Before you continue on with this video, I'd strongly suggest checking out video number 151 on my channel, which goes through all the basics of two port shunt through impedance measurements because this is exactly what we're going

to be performing on this PDN test board that we previously saw at the start of this video. In that video number 151, I

this video. In that video number 151, I talk through the two port through measurement basics, how it works, why it's useful, and this video will prove why it's useful, test equipment that you typically need for this, what impedance

ranges you can measure, what to watch out for, how we can combat ground loop errors, and much much more. So, if

you're not familiar with a two port shunt through impedance measurement basics, please go and watch that video.

I will assume that as prerequisite knowledge in terms of measurement setup because this is a two port measurement.

I of course need two probes and we also need to calibrate with an open short and load. The way I calibrate is to make a

load. The way I calibrate is to make a similar fixture to whatever my point of load will be. So right at the top here I have these two SMA ports that I can screw on and clamp on. These are

compression fit SMA ports and they just clamp on to my micro strip features below on the PCB. This construction here is to match the same construction of the point of load that I have this trace

running through and the connectors are spaced equally wide apart that I have very similar calibration standards that match again the point of load. Then I

can either populate or not populate R1.

So this could be my open short and load standards by placing different values of R1. So for short I would place a zero

R1. So for short I would place a zero ohm resistor. For an open I would place

ohm resistor. For an open I would place a large omic value resistor 1 megga or even larger 10 megga ohms. And for load, you can place a 50 or 100 mm resistor, which of course you have to adjust then when you're calibrating your instrument.

But in this way, because you're using a similar feature size to whatever you're measuring the point of load, your calibration typically is more accurate as well. You can of course do a shoulder

as well. You can of course do a shoulder sort or just leave this circuit open circuit, but you might get differently accurate measurements. So you have your

accurate measurements. So you have your calibration open, shorten load. Then

I'll move my compression fit SMA connectors down to the bottom two. This

is my actual measurement point of the point of load. As we talked about previously, we have our input voltage source that goes through if we want filtering elements. Capacitors are 1.8

filtering elements. Capacitors are 1.8 volt LDO bulk capacitance through a long length of trace. If we want more filtering elements, some load resistors and some bypass and decoupling capacitors. For this particular

capacitors. For this particular measurement, I've shorted ferro bead one and ferad bead 2. So these are pretty much just shorts. We can think of them just an extension of the length of trace. And I've removed C8 and C9. that

trace. And I've removed C8 and C9. that

we just have C7 as our bypass or decoupling capacitor at the point of load and I've kept in all the rest of the circuit. I'm using a 5V power supply

the circuit. I'm using a 5V power supply to feed in Vin and ground and we're measuring it out A and out B. That then

looks like so a kind of mangled board, but I have my vector network analyzer configured in the two port shunt through measurement connected with out A out B ports through a common mode choke to suppress ground loop errors feeding into

my vector network analyzer. I've got VN and ground connected to my power supply at 5 Vs. So normally the output voltage at U1 is 1.8 volt. It feeds through this power distribution network and we want

to measure what the impedance is at that point of load looking back towards the source. So the impedance at that point

source. So the impedance at that point with my PDN test board now powered and set up as the two port shunt through measurement. We're now in the Bodhi

measurement. We're now in the Bodhi analyzer suite which is the software accompiment to the BOD 100 vector network analyzer. I've selected my

network analyzer. I've selected my measurement method to be shunt through with the image shown on the bottom left hand side. I set up my parameters of

hand side. I set up my parameters of this measurement. I'm going to go from

this measurement. I'm going to go from 100 Hz, so close to DC, up to the maximum limit of the vector network analyzer, which is 50 MHz, nor of points 401, and my reference level currently

it's at - 10 dBm. The receiver

attenuation set to 10 dB each with a receiver bandwidth of 10 hertz. You can

see on the top I've already performed the open short load calibration where again we use the calibration test picture using various different 0603 resistors and that's already been completed. Please reference the video

completed. Please reference the video number 151 how to perform that. But it's

pretty much just click those buttons and apply the suitable calibration. With a

calibration in place, we can perform our first measurement. And this will be an

first measurement. And this will be an unpowered measurement. So there's no

unpowered measurement. So there's no power applied to the board. I'll click

single and we'll create our measurement.

I can rightclick autooptimize and see what this trace now looks like. So the

measurement is now finished. And I think this is super cool because this is actually the impedance profile of our unpowered board. We're just at the point

unpowered board. We're just at the point of load. We're looking back. the

of load. We're looking back. the

regulators and turned on our power sources and turned on and we get this impedance profile. If you've watched

impedance profile. If you've watched previous videos on also the two port shunt and characterizing multi-layer ceramic capacitors, you will recognize that this is initially capacitive impedance profile. We have this downward

impedance profile. We have this downward trending magnitude impedance profile. So

as we increase in frequency, our impedance goes down and this is due to our bulk decoupling caps. those large

electrolytics for example C5C6 are dominating to that low frequency behavior as well of as well as of course C4 and C7 remember U1 currently is not on then we can see as we go higher in

frequency at about 500 kHz or half a mehz we have an impedance dip and then a peak and then we go down in impedance we seem to have some sort of self-ressonant point and then we go into the inductive

region where we have a rising impedance magnitude characteristic with increase in frequency. So this is the board now

in frequency. So this is the board now powered off. What happens if we turn the

powered off. What happens if we turn the power on? I've turned the power on and

power on? I've turned the power on and I'm going to run another sweep. I've

actually stored this sweep in memory.

I'll click single and we can immediately see the low frequency performance has changed whereas the high frequency performance has changed as well. It's

more similar than the low frequency performance. If I now turn on my memory

performance. If I now turn on my memory of the unpowered trace, we can see these two overlaid. So now the green color,

two overlaid. So now the green color, this light green is the unpowered system. And once I turn the power on and

system. And once I turn the power on and the regulator starts becoming active, its control loop becomes active. It's

stabilizing the output voltage normally around 1.8 volts, the low frequency performance is now much different. In

fact, with the regulator on with the system powered, our impedance profile at low frequencies has a much lower impedance magnitude, which can and typically is a good thing. Then at some

crossover frequency around 10 kHz, the traces are more and more similar. These

impedance magnitude traces. You see

though there is a difference that is with a board unpowered the green trace our magnitude is actually slightly lower typically than when the board powered and this is because of the capacitor derating. Once we apply a DC bias to

derating. Once we apply a DC bias to multi-layer ceramic capacitors their capacitance actually drops which means the impedance goes up. So therefore we have a slightly higher impedance typically at least in this higher frequency range because of the DC bias

and when the board is powered on what we also see that we have some frequency shifts of course because of this change in capacitance. We might have different

in capacitance. We might have different self-ressonant frequencies and we also have some noise in the measurements. We

see that the lines aren't terribly smooth and we can change that by shaping the reference level for instance. So at

low frequencies we might want to increase the reference level because the regulator is quite strong and our signal that we inject is quite weak and then at high frequencies we might want to reduce that level. So we can do a shape level

that level. So we can do a shape level as well. If you increase the reference

as well. If you increase the reference level too high, you might distort your readings and you might get different readings because again multi-layer ceramic capacitors might derate differently with AC voltages applied a

high DC bias and so on. So try to keep your level as low as you can with a good enough signals noise ratio and not distorting your measurements. So make

sure you adjust your reference levels and see if the measurement changes. The

measurement shouldn't change in any case. Now we can see various different

case. Now we can see various different characteristic behaviors at low frequencies up to this cutoff frequency LDO. Our regulator with its control loop

LDO. Our regulator with its control loop dominates the impedance profile. And it

seems like if we take the cursor, move to the far left, our low frequency, so around 100 Hz impedance is about 26 milliohms of impedance. As we go higher and higher in frequency, 1 kHz, or we

reach our peak at 10 kHzish, we get up to impedance of about 300 milliohms. So 0.3 ohms. If you have a load that's switching at 10 kHz, you're going to have an effective series resistance of 300 milliohms, which might not be

terribly great depending on your current demands. So we can expect our voltage

demands. So we can expect our voltage noise or our output noise at that load to be highest at around 10 kohertz current draw frequency. After this LDO or regulator region which is dominated

by the control loop and the output capacitance we are still also in the bulk capacitance region before we move into the region the frequency region that is dominated or kept low by the multi-layer ceramic capacitors because

the multi-layer ceramic capacitors have a far smaller physical size. that

typically have much lower equivalent series resistance than the bulk large electrolytic capacitors and lower series inductance. That means you'll at higher

inductance. That means you'll at higher frequencies these multi-layer ceramic capacitors will dominate and we get a low impedance profile until here at around 3 1/2 to 4 MHz we reach the self-ressonant frequencies of our

multi-layer ceramic capacitor this 10 microfarad capacitor after which we then move into the inductive region where the equivalent series inductance of all our capacitors dominates. So very nicely

capacitors dominates. So very nicely we've got an impedance profile and we can correlate that to what our board has on it. Again low frequency region when

on it. Again low frequency region when the board is on is dominated by our control loop of our regulator or VRM.

Then the low frequency region is also dominated by C5C6. our bulk decoupling capacitors. As we move higher in

capacitors. As we move higher in frequency, C3 and C7 because they're smaller packages, lower ESL, lower ESR will dominate the impedance profile until we reach the ESL region where the

inductance of all of these parts dominates and our decoupling performance worsens. So overall, performing a quite

worsens. So overall, performing a quite simple measurement, as long as of course you have the gear to do so and the access points on your PCBs, you can extract the PDN profile at a specific point of load quite directly. I've now

removed one of the bulk decoupling capacitors C6. for the latter bulk

capacitors C6. for the latter bulk decoupling capacitor and let's see what the frequency response performance of the impedance profile is. Now the yellow trace is our previous measurement. So

with both bulk decoupling capacitors in place and now the new trace this red trace is with one bulk decoupling capacitor removed and we can see around the frequency range where these bulk bypass or decoupling capacitors dominate

in terms of impedance. This impedance

magnitude is now increased from the yellow trace between 10 and around 100k.

So now we have a high impedance at those frequencies which can of course be a bad thing. So now let's remove another one

thing. So now let's remove another one of these bulk decoupling capacitors and see what happens. I've now removed the second and last bulk decoupling capacitor at least in the regulator output. Let's save this measurement to

output. Let's save this measurement to new memory. And let's rerun the

new memory. And let's rerun the measurement.

And here we go. Rerunning the

measurement. And as expected now we're getting a far higher impedance in this bulk capacitor range. So around 10 to 50 10 to 100 kHz. Now we're getting more and more of this peaking because of the

interplay between the output impedance of our VRM of our LDO and the bulk capacitance in that region because we now pretty much have no bulk capacitance. And you can see impedance

capacitance. And you can see impedance magnitude is now even peaking over 1 ohm. So that frequency at around 20 25

ohm. So that frequency at around 20 25 kHz we have 1 ohm of equivalent series resistance when we have load transients at that frequency. Now let's see what happens if we remove our point of load

decoupling capacitor. Again saving this

decoupling capacitor. Again saving this data to a new memory and performing a new measurement. This is now without any

new measurement. This is now without any bulk capacitors and without the point of load 10 microfarad multi-layer ceramic capacitor. Let's perform that

capacitor. Let's perform that measurement.

Now this is pretty cool. We can quite clearly see first of all that this peaking or resonance frequency is also shifted because we've gotten rid of of another 10 microfarads of capacitance.

But of course this high frequency region which is typically dominated by these multi-layer ceramic capacitors is now effectively non-existent. We have this

effectively non-existent. We have this this parallel resonance before we immediately then go into this inductive region. We don't go down in impedance

region. We don't go down in impedance after that dip because we don't have that capacitance anymore that provides that low impedance path at these higher frequencies and therefore we have a far worse impedance profile. Of course

depends on the situation but this is why we have decoupling and bypass capacitors to keep the impedance profile low. And

of course, this isn't particularly flat either, even with all of the bypass capacitors and decoupling capacitors in place, but it's better than having no bypass capacitors as we can see here. So

quite a nice effective demonstration, I think. After having measured the power

think. After having measured the power distribution network frequency characteristics, so impedance versus frequency using the Bodi 100 vector network analyzer. I'd like to show you a

network analyzer. I'd like to show you a practical demonstration of why this is very important and what that means. for

instance, in the time domain or at that point of load. What do devices that are powered by this power distribution network see? And what problems can that

network see? And what problems can that cause? To illustrate that, we're going

cause? To illustrate that, we're going to have a very simple setup. I'm going

to use a lab power supply, normally at 5 volts, and that's just there to provide the input power to the PDN demo board to power that 1.8 volt regulator at the output of the PDN demo board. And we're

not going to have that floating anymore, but rather we can connect that to a separate board, which is pretty much just a switchable current sync. Very

simply, it's a MOSFET which has a couple load resistors in parallel which can provide a current sync to the PDN demo board. So, it's a couple hundred ohm

board. So, it's a couple hundred ohm resistors in parallel that can be shorted to ground using a FET. So,

therefore, the load that the PDN demo board sees are those resistors in parallel. And this is switchable because

parallel. And this is switchable because we can control the gate of the field effect transistors. For instance, using

effect transistors. For instance, using a signal generator. We want to use a signal generator because then we can control the frequency of switching of our load all the way from DC so constantly on off to spanning the

frequency range that we previously measured. So at 1 kHz, 10 kHz, 100 kHz,

measured. So at 1 kHz, 10 kHz, 100 kHz, we can apply this load current periodically. What we can then do is

periodically. What we can then do is feed the signal generator signal which is switching our current load to the BDN demo board. We can feed that to a

demo board. We can feed that to a trigger input of the oscilloscope. So

one oscilloscope channel will simply be the signal generator. So we can trigger off of that and that will tell us when the load current is being applied and when it isn't. Another channel of the oscilloscope will simply monitor the

output voltage at our load point at the PDN demo board. So exactly the point we took before using the BOD 100 vector network analyzer. We will measure that

network analyzer. We will measure that output voltage point at the end of our power distribution network and we can plot that voltage versus time. At DC,

our input voltage is 5 volts and our output voltage is 1.8 volt. However,

because we have impedance in our power distribution network, when we're varying the load current at various frequencies, we'll also have this noise voltage. this

AC noise voltage appear at the output which we'll be measuring with an oscilloscope. A simple illustration is

oscilloscope. A simple illustration is shown below. We have input voltage

shown below. We have input voltage source which is an ideal power source in this case a lap power supply. I'm

ignoring the cables and their impedance and we simply can replace the PDN demo board with a frequency dependent impedance or resistance term. So

depending on what frequency we switch our signal generator and therefore our current sync that impedance which is now in series with our load will change. And

we know our load, we know our load resistors, we know our load current. we

can control this switch and therefore we expect at the output a now frequency dependent voltage term. So not just 1.8 volts but a 1.8 volts DC term minus the voltage drop caused by a power

distribution network. So minus Z of F

distribution network. So minus Z of F times our load current. And this way we can infer what Z of F is if we know our output voltage that it's measured. If we

know our DC voltage and we know our load resistance. So this would be another way

resistance. So this would be another way of measuring the impedance of our power distribution network. But more

distribution network. But more interestingly I find because we already have the power distribution network profile is the real effects the power distribution network and its impedance presents at different frequencies and

how that plays a part in the actual noise voltage seen then at the point of load. So if that's a microcontroller

load. So if that's a microcontroller power pin an FPJ power pin or whatever you'll see that at different frequencies we get different noise voltages depending on the impedance profile of a power distribution network. And I find

this is super interesting and a super cool result as we'll see in just a second. Therefore, if we have larger

second. Therefore, if we have larger impedances at certain frequencies and for instance, our MCU or FPJ is trying to draw a lot of current periodically or with transients, then of course that impedance will play a part and if we get

too large of a voltage drop, we might get brown outs. We might get EMI and signal integrity issues. So, that's why this is so important. But now, let's move over to the lab setup. It's a very

simple, very crude test setup. All I'm

doing is taking our usual PDN2 port test board. Taking one of the SMA channels,

board. Taking one of the SMA channels, feeding that directly into channel one of my oscilloscope, and that's to monitor the output voltage noise. I'm

powering this board using the input and ground leads from a Ryore power supply set at 5 Vs. And the outputs I've just soldered on directly via some cables to a spare board I had which had a FET and

a couple of load resistors which I'm using as my switchable current source or current sync. And that's been driven by

current sync. And that's been driven by a Sigland wave generator that's connected to my oscilloscope. Just for

completeness sake, here's this oscilloscope I'm using. This is a four channel Sigland 2 GHz scope. Again,

channel one will be the yellow trace, which is my voltage noise. Channel 2

will be a trigger from my wavegen. And

the wavegen I'm using is the Sigland SAG wave generator, which plugs in via USB to my oscilloscope and can also be controlled by the oscilloscope, and its output again is split. One goes to channel 2 of my oscilloscope, and

another goes to the switchable current sync, which is just a fet with a couple of resistors connected to the output of the PDM test board. Now that we've just seen the lab setup for our time domain experiment to monitor the voltage noise

at the output of our power distribution network. Here's the control interface

network. Here's the control interface which I've connected to to my oscilloscope using an Ethernet interface. I've got two channels set up.

interface. I've got two channels set up.

Channel one as yellow trace is showing the voltage noise at the output and channel two is just my trigger input from my signal generator. So the signal generator controls the feds that turn on and off the load resistors to ground and

therefore provide a load to a power distribution network. and channel one

distribution network. and channel one monitors the output voltage noise. If I

go to utility wavegen, I can set up my signal generator. I'm going to do a wave

signal generator. I'm going to do a wave type of sign because that is the purest frequency content compared to running at for instance a square or trapezoidal wave where we have more more harmonics.

So running this as a sine wave lets me extract more closely the frequency profile at what happens at a specific frequency rather than a sum of different frequencies. So wavegen I'm going to

frequencies. So wavegen I'm going to change my frequency. We can just start at 100 hertz. So I'm going to type in 100. Enter. My amplitude is 3 volts P2P

100. Enter. My amplitude is 3 volts P2P just to get these MOSFETs to turn on with an offset of 1.5 volts. So my

voltage swing is between 0 and 3 volt.

And my amp load is high Z because I'm just simply driving the gate of a FET.

Now if I enable the WaveGen, my signal generator, this is now with a 100 Hz sine wave generating the current load signal. This is this pink trace at the

signal. This is this pink trace at the top. I've shifted it up a bit so they're

top. I've shifted it up a bit so they're not overlapping. And the bottom the

not overlapping. And the bottom the yellow trace which is centered around a mean of zero because this is an AC coupled signal. We're just interested in

coupled signal. We're just interested in the voltage noise. This is sitting on top of the 1.8 volt DC output of the power distribution network. And this is really cool because we can nicely see what happens when the current source

engages. So when we go from the FET off

engages. So when we go from the FET off at the lowest point of the sine wave to the FET fully on at the highest point of the sine wave. So on the rising transient when we're applying a load current or we want to draw more load

current, we can see our supply rail in the yellow trace below it actually dips down before it then settles tries to go back to the normal 1.8 8 volts. Then

once we disengage the load current, so we go from a peak high of our sine wave back to zero when we're turning off the FET, the voltage of the output noise now overshoots the other way. And this is because again we have this series

resistance which is a frequency dependent term. So at 100 hertz this

dependent term. So at 100 hertz this series resistor has a particular value and we still have that fixed load current value and therefore we will get a voltage drop as the load current demand changes. At DC our series

demand changes. At DC our series resistance is whatever the DC resistance is we measure of our power distribution network. So typically smaller than the

network. So typically smaller than the AC impedance. So that's why we return

AC impedance. So that's why we return back to the nominal 1.8 volt. So this is quite cool to see that the current demand because of the non idealities of terror distribution network projects

noise or induces noise onto our voltage rail as we can see here. And I've added a couple measurements at the bottom. So

I've measured peakto peak noise the max and min pertubations around the mean value of 1.8 volts as well as the RMS noise. And we can see here RMS noise is

noise. And we can see here RMS noise is about 4.85 85 m volts and we can see peakto peak is about 27 m volts 400 htz load pertubation and for this particular load current. Now if I go back to the

load current. Now if I go back to the wavegen and change my frequency let's say to 1 kHz let's see what happens with the noise signature and immediately as I change it we have to change the scales we change the time base and immediately

as I now with the time base adjusted we can see the noise is actually much worse now we have an RMS noise of about 40 ms and a peakto peak ripple of about 108

molts. So compare that to a 100 Hz case

molts. So compare that to a 100 Hz case now going up to 1 kHz, we have far more voltage noise for the same load current but at a different load current frequency. Now this should all make

frequency. Now this should all make sense because if we go back to the Bodhi analyzer suite and look at our impedance profile around 100 Hz, we had a lower impedance than if we go to 1 kHz. Now if

we go to 10 kHz, this should be our peak of our impedance profile at least for this somewhat low frequency range. So if

we go to 10 kHz, we expect an even worse voltage noise profile at the output. So,

let's go back to the wavegen. Change the

frequency to 10 kHz. And I've adjusted my time base again. And here we can see we're getting an even higher RMS noise magnitude with a different noise profile and a higher peak to peak of course because now we are in this high

impedance range on our PDN impedance curve. So now our impedance curve for

curve. So now our impedance curve for this sine wave is sitting approximately at this 10 kHz point here. We have our impedance magnitude and therefore we expect a higher voltage drop and a higher voltage noise because of that

impedance profile. And that's exactly

impedance profile. And that's exactly what we can see here. Now, as we move further and further along the x-axis, so increasing in frequency, we should see our noise voltage drop again. Now, going

up to 100 kHz, our noise voltage will reduce again because we are following this impedance profile that we measured before. So, now we have a far lower

before. So, now we have a far lower noise voltage as we can see here. What

we can also do is not just provide a sine wave but we could also go to a square wave for instance and see that the noise characteristics change because now this is a superp position of several sine waves and we get addition of the

impedances at those different frequencies depending on the harmonic content. So if I go back to 1 kHz,

content. So if I go back to 1 kHz, change my wave gen now to a square wave, we can see that we have a different noise profile as well. Even though the fundamental is a square wave which might

be more characteristic of a digital system where we have these pulses or these transients rather than sinocidal signals but the square wave or the traversal wave can be of course represented by a furious series of odd

harmonics and therefore we get a superp position of our impedance profile frequency points and that then builds our impedance at that particular frequency at that particular frequency for this particular square wave. And

here this again illustrates quite nicely that at a current demand so the FedEx switching on where we have this rising edge our voltage rail dips because now we have this increased current demand and our impedance is a certain amount

our series impedance of our power distribution network and that's why we got a voltage dip before DC we settle back to 1.8 8 volts and we can also see there is some resonance in this because of the impedance profile. So it's not a

critically damped system. This is

actually an underdamped system. The

content of this ringing depends on the impedance profile as well. So what you could do is you could sweep through all these different frequencies 1 kHz, 10 kHz and so on. Calculate the RMS voltage noise and divide that by your load

current and get an approximation for your power distribution impedance. But

of course we can automate that. I'd love

to show you how to do that other than using a BOD 100. I can of course automate this procedure rather than manually stepping through with my function generator recording the measurements for example in an Excel

sheet I can use the built-in bodhypot feature of my particular scope which is also connected of course to the function generator so I've opened up the bodhip plot interface I can configure my inputs outputs now of course the actual

transfer function the actual output magnitude doesn't terally mean very much because my output signal is that of the function generator which is controlling the feds which controlling the current and my output signal is essentially the

average or the RMS magnitude measured at the output by this bodhi tool. But

hopefully we can see that the curve that is traced out follows our PDN impedance profile that we measured early on using the vector network analyzer. So in terms of setup, my device under test input I have on my channel 2 which is basically

my function generator output. My device

under test output which is the voltage noise of my regulator and power distribution network. I'm measuring with

distribution network. I'm measuring with channel one. As before I'm doing a

channel one. As before I'm doing a frequency sweep from 100 Hz to 5 MHz.

same amplitude and offset settings as before. And then I can click operation

before. And then I can click operation start or on and this will perform this measurement automatically. And this does

measurement automatically. And this does of course take a while, but I've pulled up the PDN measurements we had on the right hand side. What should happen is that we get the same kind of curve shape using our body plot tool on the left

hand side as we did using the vector network analyzer. We're doing a very

network analyzer. We're doing a very very similar measurement where measuring the output voltage noise generated by our current draws.

and here we have now have the measurement finished. And this pretty

measurement finished. And this pretty much has the same shape as our BOD 100 measurement using the vector neo analyzer. We are doing essentially the

analyzer. We are doing essentially the same measurement just in a different way. Then we're applying a current load

way. Then we're applying a current load stimulus and measuring the output. And

that transfer function V over I is our impedance profile. And we have the same

impedance profile. And we have the same rising characteristic. We're peing at

rising characteristic. We're peing at around 10 kHz. Afterwards, we're

dropping off. We have the effects of series and parallel resonances. And also

for the multi-layer ceramic capacitors a bit further on.

The cool thing is we have shown two different methods of extracting essentially the same information and we verified what effect our PDN impedance has on the ripple effects seen at a particular point on the printed circuit

board at a particular point at the power distribution network. So even if you

distribution network. So even if you don't have a bod 100, you can also perform these measurements using a signal generator, a current sync, and an oscilloscope. Lastly, I'd like to end

oscilloscope. Lastly, I'd like to end this video by providing a very simple LT spice simulation that aims to capture the main parts of the power distribution network. Here I've broken down my power

network. Here I've broken down my power distribution network test board into very simple elements. For instance, on the left hand side we have a low dropout regulator model. Then I have a tiny bit

regulator model. Then I have a tiny bit of trace, a capacitor, a bulk capacitor.

Again, another bit of trace and a bulk capacitor, a longer trace and a multi-layer ceramic capacitor. And then

my point of load we have a couple parallel resistors. I can then use this

parallel resistors. I can then use this in the simulation to perform an AC frequency simulation. provide a current

frequency simulation. provide a current source stimulus to then measure the impedance looking into the node which is at the point of the load looking back towards the source. The way I arrived at

all these models is by extracting them from manufacturer data as well as my PCB. For example, to a trace I've

PCB. For example, to a trace I've modeled my traces as series resistances and series inductances as a very very simple model. So depending on the trace

simple model. So depending on the trace length, so the longer the trace, the higher the series resistance. The longer

the trace, the higher the series inductance. Now where do you get those

inductance. Now where do you get those values from? I extracted them from Alum

values from? I extracted them from Alum Designer. If I click on a segment of

Designer. If I click on a segment of trace, let's say this 7.5 mm trace length here between these two capacitors on the right hand side, I can see the trace measurement in the properties panel. If I expand it, the resistance is

panel. If I expand it, the resistance is estimated at about 3 milliohms. If I like to get the impedance, I can go to design layer stack manager. I type in my trace geometries and I'm using a

single-ended co-planer micro strip with a width of 1.25 mm. If I click on that, go to on the right hand side properties, I can see an inductance in nanohen's per meter. So that's 290 nanohenies per

meter. So that's 290 nanohenies per meter. So per millimeter that's 0.3

meter. So per millimeter that's 0.3 nanohhen's per millimeter approximately.

And that's exactly what I've entered here. So my 7.5 mm trace turns out to

here. So my 7.5 mm trace turns out to have about 3 milliohms of resistance and 2.2 nanohen's of inductance for that short length of trace. My longer length of trace is just scaled by whatever the

length is. So 52 mm turns out to be

length is. So 52 mm turns out to be these values. Then my capacitors. I'd

these values. Then my capacitors. I'd

strongly suggest watching my multi-layer ceramic capacitor videos. I'll link that in the description box below. But a

capacitor isn't just a capacitor. A

simple equivalent model is a capacitor with a ESL, so equivalent series inductance as well as ESR, equivalent series resistance. I have particular

series resistance. I have particular capacitors on the board and this happens to be a Panasonic 47 microfarad aluminium electrolytic capacitor and I've extracted these component values from the manufacturer's website. So

pretty high ESL and pretty high equivalent series resistance. So these

are my bulk capacitors along with the connecting traces. Similarly for the

connecting traces. Similarly for the point of load where I have the multi-layer ceramic capacitor I've extracted that LCR model from Marato who makes this capacitor I've added in a tiny bit of effects of drating. So this

is a normally 10 microfarad capacitor but it's derated to let's say 8.5 microfarads for that particular DC voltage a far lower series inductance and far lower series resistance. Finally

right at the start my power source is of course grounded. It's a DC power source.

course grounded. It's a DC power source.

So at AC that's a short. Then I have my output capacitor and I have the model a very very simplified model of my linear regulator which can be represented simply by a series resistance and a

series inductance. And you can see the

series inductance. And you can see the magnitude of that series inductance is a lot larger typically than the trace inductance. To then plot impedance I've

inductance. To then plot impedance I've added in an AC current source feeding my point of load given it an AC magnitude of one. So simply measuring the voltage

of one. So simply measuring the voltage of that node then we have V= IZ I= 1.

That means the V equals Z and our impedance is simply the voltage plot at that point. I'm running my AC simulation

that point. I'm running my AC simulation from 100 Hz to 50 MHz. And now I can click run simulation. Click on the impedance point. And this is the

impedance point. And this is the impedance profile I get with my simulation. We have the low frequency

simulation. We have the low frequency performance dominated by the inductance and bulk capacitance up to the crossover frequency at around 10 kHz. Then the

decreasing impedance profile. We have a a parallel resonance, a series resonance. Then we have a multi-layer

resonance. Then we have a multi-layer ceramic capacitor self-ress resonant frequency after which we go into the equivalent series inductance part of this impedance magnitude. Plotting our

simulation on the left hand side to our real world measurements on the right hand side. The overall shape is a very

hand side. The overall shape is a very good fit. We have the same trends in

good fit. We have the same trends in terms of impedance magnitude versus frequency. Also in terms of phase the

frequency. Also in terms of phase the phase looks very similar. Of course,

some of the some of the peak frequencies and also the magnitudes might be slightly off, but I just wanted to show that using rather simple models and very simple approximations of components,

traces, capacitors, VRMS, you can get a very basic simulation that approximates the real impedance magnitude just by using the manufacturer data as shown here. So, it's nice that these two

here. So, it's nice that these two curves actually line up quite well for the most points. There are tiny bits of offset of course and higher resolution the actual measurement than our lower fidelity spice model we have here but I

think it demonstrates quite nicely that even with a simple simulation you can approximate these PDN curves and also how to then show the impedance versus frequency using LT spice. Thank you very much for watching this video. I hope it

was useful and I hope it gave you an insight into the real world practical considerations when measuring power distribution networks on real world PCBs. also what effect then the PDN

PCBs. also what effect then the PDN impedance characteristic has on the voltage noise performance at a point of load on a PCB and also how you can perform very simple simulations and emulations of power distribution

networks using LT Spice. If you like the video, please leave a like, a comment if you have any questions and don't forget to subscribe to stay up to date with any latest PCB hardware design and embedded systems videos. Thanks again for

systems videos. Thanks again for watching and I hope to see you in the next one. Bye-bye.

next one. Bye-bye.